Formal Verification Techniques for Digital Systems

In deep submicron technology, a large and complex system that has a wide variety of functionalities has been integrated on a single chip. However, it is getting too harder and harder to identify all design bugs in such a large and complex system. If design bugs caused by the initial specification are identified at lower level of abstraction, we are required redesign of the system from the initial specification to fix the bugs. As a result, the productivity of the system will be decreased. In current system designs, the verification time to check whether a design is correct or not takes 80% of the overall time. Therefore, the development of verification techniques in each level of abstraction is indispensable. Logic simulation is a widely used technique for the verification of a design. It simulates the output value for given input patterns. However, because the quality of verification deeply depends on given input patterns, there is a possibility that design bugs exist that cannot be identified during logic simulation. Because the number of required input patterns is exponentially increased when the size of a design is increased, it is impossible to verify the overall design by logic simulation. To solve this problem, the development of formal verification techniques is indispensable. In formal verification, specification and design are translated into mathematical models. Formal verification techniques verify a design by proving the correctness mathematically. Therefore, formal verification techniques can verify the overall design exhaustively. Formal verification techniques have been widely used for the verification of software designs. These techniques are then extended for the verification of hardware designs. In particular, after the development of binary decision diagram (BDD), the ability of formal verification techniques is significantly